MC9S12T64 Datasheet, PDF (540/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
After reset, this pin becomes the dedicated serial interface pin for the
BDM module.
The BDM serial interface is timed using the clock selected by the
CLKSW bit in the status register (see BDM Status Register (BDMSTS)).
This clock will be referred to as the target clock in the following
explanation.
The BDM serial interface uses a clocking scheme in which the external
host generates a falling edge on the BKGD pin to indicate the start of
each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB)
first at 16 target clock cycles per bit. The interface times out if 512 clock
cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip
active pull-up that is enabled at all times. It is assumed that there is an
external pullup and that drivers connected to BKGD do not typically drive
the high level. Since R-C rise time could be unacceptably long, the target
system and host provide brief driven-high (speedup) pulses to drive
BKGD to a logic 1. The source of this speedup pulse is the host for
transmit cases and the target for receive cases.
Diagrams in Figure 104, Figure 105, and Figure 106 show timing of
bit-time cases in single wire mode. Each case begins when the host
drives the BKGD pin low to generate a falling edge. Since the host and
target are operating from separate clocks, it can take the target MCU up
to one full clock cycle to recognize this edge. The target measures
delays from this perceived start of the bit time while the host measures
delays from the point it actually drove BKGD low to start the bit up to one
target clock cycle earlier. Synchronization between the host and target
is established in this manner at the start of every bit time.
Figure 104 shows an external host transmitting a logic 1 and transmitting
a logic 0 to the BKGD pin of a target system. The host is asynchronous
to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as
the beginning of the bit time. Ten target clock cycles later, the target
senses the bit level on the BKGD pin. Internal glitch detect logic requires
MC9S12T64Revision 1.1.1
540
Fast Background Debug Module (FBDM)
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