MC9S12T64 Datasheet, PDF (303/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Functional Description
Computer
Operating
Properly
Watchdog (COP)
OSCCLK
WAIT(COPWAI),
STOP(PSTP,PCE),
COP enable
CR[2:0]
0:0:0
gating condition
= Clock Gate
CR[2:0]
0:0:1
÷ 16384
÷4
0:1:0
÷4
0:1:1
÷4
1:0:0
÷4
1:0:1
÷2
1:1:0
÷2
1:1:1
COP TIMEOUT
Figure 51 Clock Chain for COP
The COP (free running watchdog timer) enables the user to check that
a program is running and sequencing properly. When the COP is being
used, software is responsible for keeping the COP from timing out. If the
COP times out it is an indication that the software is no longer being
executed in the intended sequence; thus a system reset is initiated (see
Computer Operating Properly Watchdog (COP) Reset in page 321). The
COP runs with a gated OSCCLK (see Figure 51). Three control bits in
the COPCTL register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this
order) to the ARMCOP register during the selected time-out period.
Once this is done, the COP time-out period is restarted. If the program
fails to do this and the COP times out, the part will reset. Also, if any
value other than $55 or $AA is written, the part is immediately reset.
Window COP operation is enabled by setting WCOP in the COPCTL
register. In this mode, writes to the ARMCOP register to clear the COP
timer must occur in the last 25% of the selected time-out period. A
premature write will immediately reset the part.
MOTOROLA
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1
303