MC9S12T64 Datasheet, PDF (302/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
CLOCK OK
CM_Fail
POR | LVDR
or
Exit_Full_Stop
num=0
check window
OSCCLK ^no
OK?
yes
Clock Monitor Reset
Enter SCM
yes
num=num+1
yes
no
num<50 ?
no
SCM
active?
yes
SCME=1 ^no
?
SCM
active?
yes _{Switch to OSCCLK}
num=50
no
Exit SCM
num: Number of check windows performed.
Figure 50 Sequence for Clock Quality Check
NOTE:
Remember that in parallel to additional actions caused by Self Clock
Mode or Clock Monitor Reset¹ handling the clock quality checker
continues to check the OSCCLK signal.
NOTE:
The Clock Quality Checker enables the PLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running PLL (f_SCM) and an active
VREG during Pseudo-Stop Mode or Wait Mode
1. A Clock Monitor Reset will always set the SCME bit to logical’1’
MC9S12T64Revision 1.1.1
302
Clocks and Reset Generator (CRG)
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