MC9S12T64 Datasheet, PDF (292/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Table 52 COP Watchdog Rates⁽¹⁾
CR2
CR1
CR0
Divide
OSCCLK by
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OFF
2 ¹⁴
2 ¹⁶
2 ¹⁸
2 ²⁰
2 ²²
2 ²³
2 ²⁴
1. Times are referenced from the previous
COP time-out reset (writing $55/$AA to
the ARMCOP register)
CRG COP Timer
Arm/Reset
Register
(ARMCOP)
This register is used to restart the COP time-out period.
Address Offset: $003F
Bit 7
6
5
4
3
2
1
0
Read:
0
0
0
0
0
0
0
0
Write: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
0
0
0
0
0
0
0
0
Read: always reads $00.
Write: anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has
no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following
applies:
MC9S12T64Revision 1.1.1
292
Clocks and Reset Generator (CRG)
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