MC9S12T64 Datasheet, PDF (49/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Instruction Set Overview
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Machine
Mode Coding (Hex)
STS opr8a
STS opr16a
STS oprx0_xysppc
STS oprx9,xysppc
STS oprx16,xysppc
STS [D,xysppc]
STS [oprx16,xysppc]
Store SP
(SP_H:SP_L)⇒M:M+1
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5F dd
7F hh ll
6F xb
6F xb ff
6F xb ee ff
6F xb
6F xb ee ff
STX opr8a
STX opr16a
STX oprx0_xysppc
STX oprx9,xysppc
STX oprx16,xysppc
STX [D,xysppc]
STX [oprx16,xysppc]
Store X
(X_H:X_L)⇒M:M+1
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5E dd
7E hh ll
6E xb
6E xb ff
6E xb ee ff
6E xb
6E xb ee ff
STY opr8a
STY opr16a
STY oprx0_xysppc
STY oprx9,xysppc
STY oprx16,xysppc
STY [D,xysppc]
STY [oprx16,xysppc]
Store Y
(Y_H:Y_L)⇒M:M+1
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5D dd
7D hh ll
6D xb
6D xb ff
6D xb ee ff
6D xb
6D xb ee ff
SUBA #opr8i
SUBA opr8a
SUBA opr16a
SUBA oprx0_xysppc
SUBA oprx9,xysppc
SUBA oprx16,xysppc
SUBA [D,xysppc]
SUBA [oprx16,xysppc]
Subtract from A
(A)–(M)⇒A
or (A)–imm⇒A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
80 ii
90 dd
B0 hh ll
A0 xb
A0 xb ff
A0 xb ee ff
A0 xb
A0 xb ee ff
SUBB #opr8i
SUBB opr8a
SUBB opr16a
SUBB oprx0_xysppc
SUBB oprx9,xysppc
SUBB oprx16,xysppc
SUBB [D,xysppc]
SUBB [oprx16,xysppc]
Subtract from B
(B)–(M)⇒B
or (B)–imm⇒B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C0 ii
D0 dd
F0 hh ll
E0 xb
E0 xb ff
E0 xb ee ff
E0 xb
E0 xb ee ff
SUBD #opr16i
SUBD opr8a
SUBD opr16a
SUBD oprx0_xysppc
SUBD oprx9,xysppc
SUBD oprx16,xysppc
SUBD [D,xysppc]
SUBD [oprx16,xysppc]
Subtract from D
(A:B)–(M:M+1)⇒A:B
or (A:B)–imm⇒A:B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
83 jj kk
93 dd
B3 hh ll
A3 xb
A3 xb ff
A3 xb ee ff
A3 xb
A3 xb ee ff
SWI
Software interrupt; (SP)–2⇒SP
INH
3F
RTN_H:RTN_L⇒M_SP:M_SP+1
(SP)–2⇒SP; (Y_H:Y_L)⇒M_SP:M_SP+1
(SP)–2⇒SP; (X_H:X_L)⇒M_SP:M_SP+1
(SP)–2⇒SP; (B:A)⇒M_SP:M_SP+1
(SP)–1⇒SP; (CCR)⇒M_SP;1⇒I
(SWI vector)⇒PC
*The CPU also uses VSPSSPSsP for hardware interrupts and unimplemented opcode traps.
TAB
Transfer A to B; (A)⇒B
INH
18 0E
TAP
Transfer A to CCR; (A)⇒CCR
INH
B7 02
Assembled as TFR A, CCR
TBA
Transfer B to A; (B)⇒A
INH
18 0F
Access Detail
PW
PWO
PW
PWO
PWP
PIfW
PIPW
PW
PWO
PW
PWO
PWP
PIfW
PIPW
PW
PWO
PW
PWO
PWP
PIfW
PIPW
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
VSPSSPSsP*
OO
P
OO
SXHINZVC
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
–––1––––
––––∆∆0–
∆⇓∆∆∆∆∆∆
––––∆∆0–
MOTOROLA
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1
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