MC9S12T64 Datasheet, PDF (473/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Functional Description
Although the SPI is capable of duplex operation, some SPI peripherals
are capable of only receiving SPI data in a slave mode. For these simpler
devices, there is no serial data out pin.
NOTE:
When peripherals with duplex capability are used, take care not to
simultaneously enable two receivers whose serial outputs drive the
same system slave’s serial data output line.
As long as no more than one slave device drives the system slave’s
serial data output line, it is possible for several slaves to receive the
same transmission from a master, although the master would not
receive return information from all of the receiving slaves.
If the CPHA bit in SPI control register 1 is clear, odd numbered edges on
the SCK input cause the data at the serial data input pin to be latched.
Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB of the SPI shifter.
If the CPHA bit is set, even numbered edges on the SCK input cause the
data at the serial data input pin to be latched. Odd numbered edges
cause the value previously latched from the serial data input pin to shift
into the LSB of the SPI shifter.
NOTE:
In slave mode, the control bits CPHA and CPOL of the SPI should be
configured only when SPI is disabled else it may lead to incorrect data
transfer. If the SPI is disabled, e.g. for configuration purpose, the
dedicated SPI pins become GPIO pins. Care must be taken to avoid
driver collisions. As recommended action, GPIO pins should be
configured as high impedance inputs, before disabling the SPI.
When CPHA is set, the first edge is used to get the first data bit onto the
serial data output pin. When CPHA is clear and the SS input is low (slave
selected), the first bit of the SPI data is driven out of the serial data output
pin. After the eighth shift, the transfer is considered complete and the
received data is transferred into the SPI data register. To indicate
transfer is complete, the SPIF flag in the SPI status register is set.
NOTE: There is an errata information about CPHA=1 transfer format in slave
mode. See MC9S12T64 Errata Sheet for details.
MOTOROLA
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1
473