MC9S12T64 Datasheet, PDF (413/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Functional Description
16-bit Main Timer
PTn
Edge detector
Delay counter
TCn Input Capture Reg.
Set CnF Interrupt
TCnH I.C. Holding Reg. BUFEN • LATQ • TFMOD
Figure 73 Interrupt Flag Setting
IC Channels
Non-Buffered IC
Channels
Buffered IC
Channels
The IC channels are composed of four standard IC registers and four
buffered IC channels.
An IC register is empty when it has been read or latched into the
holding register.
A holding register is empty when it has been read.
The main timer value is memorized in the IC register by a valid input pin
transition.
If the corresponding NOVWx bit of the ICOVW register (see page 400)
is cleared, with a new occurrence of a capture, the contents of IC register
are overwritten by the new value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register cannot be written unless it is empty.
This will prevent the captured value to be overwritten until it is read.
There are two modes of operations for the buffered IC channels.
• IC Latch Mode:
MOTOROLA
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1
413