MC9S12T64 Datasheet, PDF (38/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Source Form
ASL opr16aSame as LSL
ASL oprx0_xysp
ASL oprx9,xysppc
ASL oprx16,xysppc
ASL [D,xysppc]
ASL [oprx16,xysppc]
ASLASame as LSLA
ASLBSame as LSLB
ASLDSame as LSLD
ASR opr16a
ASR oprx0_xysppc
ASR oprx9,xysppc
ASR oprx16,xysppc
ASR [D,xysppc]
ASR [oprx16,xysppc]
ASRA
ASRB
BCC rel8Same as BHS
BCLR opr8a, msk8
BCLR opr16a, msk8
BCLR oprx0_xysppc, msk8
BCLR oprx9,xysppc, msk8
BCLR oprx16,xysppc, msk8
BCS rel8Same as BLO
BEQ rel8
BGE rel8
BGND
BGT rel8
BHI rel8
BHS rel8Same as BCC
BITA #opr8i
BITA opr8a
BITA opr16a
BITA oprx0_xysppc
BITA oprx9,xysppc
BITA oprx16,xysppc
BITA [D,xysppc]
BITA [oprx16,xysppc]
BITB #opr8i
BITB opr8a
BITB opr16a
BITB oprx0_xysppc
BITB oprx9,xysppc
BITB oprx16,xysppc
BITB [D,xysppc]
BITB [oprx16,xysppc]
Table 4 Instruction Set Summary (Continued)
Operation
Address
Machine
Mode Coding (Hex)
Arithmetic shift left M
C b7
0
b0
Arithmetic shift left A
Arithmetic shift left B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
78 hh ll
68 xb
68 xb ff
68 xb ee ff
68 xb
68 xb ee ff
48
58
Arithmetic shift left D
INH
59
•••
•••
0
C b7 A b0 b7 B b0
Arithmetic shift right M
b7
b0 C
Arithmetic shift right A
Arithmetic shift right B
Branch if C clear; if C=0, then
(PC)+2+rel⇒PC
Clear bit(s) in M; (M)•mask byte⇒M
Branch if C set; if C=1, then
(PC)+2+rel⇒PC
Branch if equal; if Z=1, then
(PC)+2+rel⇒PC
Branch if ≥ 0, signed; if N⊕V=0, then
(PC)+2+rel⇒PC
Enter background debug mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
REL
DIR
EXT
IDX
IDX1
IDX2
REL
REL
REL
INH
77 hh ll
67 xb
67 xb ff
67 xb ee ff
67 xb
67 xb ee ff
47
57
24 rr
4D dd mm
1D hh ll mm
0D xb mm
0D xb ff mm
0D xb ee ff mm
25 rr
27 rr
2C rr
00
Branch if > 0, signed; if Z | (N⊕V)=0,
then (PC)+2+rel⇒PC
Branch if higher, unsigned; if
C | Z=0, then (PC)+2+rel⇒PC
Branch if higher or same,unsigned; if
C=0, then (PC)+2+rel⇒PC
Bit test A; (A)•(M)
or (A)•imm
Bit test B; (B)•(M)
or (B)•imm
REL
REL
REL
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
2E rr
22 rr
24 rr
85 ii
95 dd
B5 hh ll
A5 xb
A5 xb ff
A5 xb ee ff
A5 xb
A5 xb ee ff
C5 ii
D5 dd
F5 hh ll
E5 xb
E5 xb ff
E5 xb ee ff
E5 xb
E5 xb ee ff
Access Detail
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
O
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
PPP (branch)
P (no branch)
rPwO
rPwP
rPwO
rPwP
frPwPO
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
VfPPP
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
SXHINZVC
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––––––
––––∆∆0–
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
––––∆∆0–
––––∆∆0–
MC9S12T64Revision 1.1.1
38
Central Processing Unit (CPU)
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