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MC9S12T64 Datasheet, PDF (358/608 Pages) Motorola, Inc – Specification
Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
edge. When the channel is disabled (PWMEx=0), the counter for the
channel does not count.
PWM Polarity
Each channel has a polarity bit to allow starting a waveform cycle with a
high or low signal. This is shown on the block diagram as a mux select
of either the Q output or the Q output of the PWM output flip flop in Figure
61. When one of the bits in the PWMPOL register is set, the associated
PWM channel output is high at the beginning of the waveform, then goes
low when the duty count is reached. Conversely, if the polarity bit is zero,
the output starts low and then goes high when the duty count is reached.
PWM Period and
Duty
Dedicated period and duty registers exist for each channel and are
double buffered so that if they change while the channel is enabled, the
change will NOT take effect until one of the following occurs:
• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled
In this way, the output of the PWM will always be either the old waveform
or the new waveform, not some variation in between. If the channel is
not enabled, then writes to the period and duty registers will go directly
to the latches as well as the buffer.
A change in duty or period can be forced into effect ‘immediately’ by
writing the new value to the duty and/or period registers and then writing
to the counter. This forces the counter to reset and the new duty and/or
period values to be latched. In addition, since the counter is readable it
is possible to know where the count is with respect to the duty value and
software can be used to make adjustments
CAUTION: When forcing a new period or duty into effect immediately, an irregular
PWM cycle can occur.
NOTE: Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time.
MC9S12T64Revision 1.1.1
358
Pulse Width Modulator (PWM8B8C)
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