MC9S12T64 Datasheet, PDF (312/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Wake-up from Stop-Mode also depends on the setting of the PSTP bit.
Core req’s
Stop Mode.
Clear PLLSEL,
Disable PLL
Exit Wait w.
ext.RESET
Wait Mode left
due to external reset
Enter
Stop Mode
no
no
Exit Stop w. ^no
CMR
SCME=1
?
yes
Exit
Stop Mode
INT
?
yes
CLOCK
OK
?
yes
Exit
Stop Mode
no
yes
PSTP=1
?
CME=1
no
?
yes
no
CM fail
?
yes
Exit Stop w.
no
CMR
SCME=1
?
yes
Generate
SCM Interrupt
(Wakeup from Stop)
no
SCMIE=1
?
yes
Exit
Stop Mode
Enter
SCM
Enter
SCM
no
INT
?
yes
Exit
Stop Mode
no
SCM=1
?
yes
Enter
SCM
Clocks
OK
?
Stands for a Clock Quality Check
Continue w.
normal OP
Figure 54 Stop Mode Entry/Exit Sequence
MC9S12T64Revision 1.1.1
312
Clocks and Reset Generator (CRG)
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