MC9S12T64 Datasheet, PDF (32/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
When the I bit is clear and a maskable interrupt request occurs, the
CPU stacks the cleared I bit. It then automatically sets the I bit in the
CCR to prevent other maskable interrupt requests during the interrupt
service routine.
An RTI instruction at the end of the interrupt service routine restores
the cleared I bit to the CCR, reenabling maskable interrupt requests.
The I bit can be cleared within the service routine, but implementing
a nested interrupt scheme requires great care, and seldom improves
system performance.
1 = Maskable interrupt requests disabled
0 = Maskable interrupt requests enabled
N — Negative Bit
The N bit is set when the MSB of the result is set. N is most commonly
used in two’s complement arithmetic, where the MSB of a negative
number is one and the MSB of a positive number is zero, but it has
other uses. For instance, if the MSB of a register or memory location
is used as a status bit, the user can test the bit by loading an
accumulator.
1 = MSB of result set
0 = MSB of result clear
Z — Zero Bit
The Z bit is set when all the bits of the result are zeros. Compare
instructions perform an internal implied subtraction, and the condition
codes, including Z, reflect the results of that subtraction. The INX,
DEX, INY, and DEY instructions affect the Z bit and no other condition
bits. These operations can only determine = and ≠.
1 = Result all zeros
0 = Result not all zeros
V — Overflow Bit
The V bit is set when a two’s complement overflow occurs as a result
of an operation.
1 = Overflow
0 = No overflow
C — Carry Bit
MC9S12T64Revision 1.1.1
32
Central Processing Unit (CPU)
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