MC9S12T64 Datasheet, PDF (313/608 Pages) Motorola, Inc – Specification

Wake-up from
Pseudo-Stop
(PSTP=1)
Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Low Power Options
Wake-up from Pseudo-Stop is the same as wake-up from Wait-Mode.
There are also five different scenarios for the CRG to restart the MCU
from Pseudo-Stop Mode:
• External Reset
• Clock Monitor Fail
• Wake-up Interrupt
If the MCU gets an external reset during Pseudo-Stop Mode active, the
CRG asynchronously restores all configuration bits in the register space
to its default settings and starts the reset generator. After completing the
reset sequence processing begins by fetching the normal reset vector.
Pseudo-Stop Mode is left and the MCU is in Run Mode again.
If the clock monitor is enabled (CME=1) the MCU is able to leave
Pseudo-Stop Mode when loss of oscillator/external clock is detected by
a clock monitor fail. If the SCME bit is not asserted the CRG generates
a clock monitor fail reset (CMR). The CRG’s behavior for CMR is the
same compared to external reset, but another reset vector is fetched
after completion of the reset sequence. If the SCME bit is asserted the
CRG generates a SCM interrupt if enabled (SCMIE=1). After generating
the interrupt the CRG enters Self-Clock Mode and starts the clock quality
checker (see Clock Quality Checker in page 301). Then the MCU
continues with normal operation. If the SCM interrupt is blocked by
SCMIE=0, the SCMIF flag will be asserted but the CRG will not wake-up
from Pseudo-Stop Mode.
If any other interrupt source (e.g. RTI) triggers exit from Pseudo-Stop
Mode, the MCU immediately continues with normal operation. Because
the PLL has been powered-down during Stop-Mode the PLLSEL bit is
cleared and the MCU runs on OSCCLK after leaving Stop-Mode. The
software must set the PLLSEL bit again, in order to switch system and
core clocks to the PLLCLK.
Table 55 summarizes the outcome of a clock loss while in Pseudo-Stop
Mode.
MOTOROLA
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1
313