MC9S12T64 Datasheet, PDF (316/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Table 55 Outcome of Clock Loss in Pseudo-Stop Mode (Continued)
CME
1
SCME
1
SCMIE CRG Actions
Clock failure -->
- VREG enabled,
- PLL enabled,
- SCM activated,
- Start Clock Quality Check,
- SCMIF set.
1
SCMIF generates Self Clock Mode wakeup interrupt.
- Exit Pseudo-Stop Mode in SCM using PLL clock (f_SCM) as system clock,
- Continue to perform a additional Clock Quality Checks until OSCCLK
is o.k. again.
Wake-up from Full
Stop (PSTP=0)
The MCU requires an external interrupt or an external reset in order to
wake-up from Stop-Mode.
If the MCU gets an external reset during Full Stop Mode active, the CRG
asynchronously restores all configuration bits in the register space to its
default settings and will perform a maximum of 50 clock check windows
(see Clock Quality Checker in page 301). After completing the clock
quality check the CRG starts the reset generator. After completing the
reset sequence processing begins by fetching the normal reset vector.
Full Stop-Mode is left and the MCU is in Run Mode again.
If the MCU is woken-up by an interrupt, the CRG will also perform a
maximum of 50 clock check windows (see Clock Quality Checker in
page 301). If the clock quality check is successful, the CRG will release
all system and core clocks and will continue with normal operation. If all
clock checks within the Timeout-Window are failing, the CRG will switch
to Self-Clock Mode or generate a clock monitor reset (CMR) depending
on the setting of the SCME bit in the PLLCTL register (page 286). If the
SCME bit is cleared, CRG generates a Clock Monitor Reset; otherwise,
it enters Self Clock Mode.
Because the PLL has been powered-down during Stop-Mode the
PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving
Stop-Mode. The software must manually set the PLLSEL bit again, in
order to switch system and core clocks to the PLLCLK.
MC9S12T64Revision 1.1.1
316
Clocks and Reset Generator (CRG)
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