MC9S12T64 Datasheet, PDF (407/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
If the RDMCL bit in MCCTL register (see page 396) is cleared, reads of
the MCCNT register will return the present value of the count register. If
the RDMCL bit is set, reads of the MCCNT will return the contents of the
load register.
If a $0000 is written into MCCNT and modulus counter while LATQ and
BUFEN in ICSYS register are set, the input capture and pulse
accumulator registers will be latched.
With a $0000 write to the MCCNT, the modulus counter will stay at zero
and does not set the MCZF flag in MCFLG register.
If modulus mode is enabled (MODMC=1), a write to this address will
update the load register with the value written to it. The count register will
not be updated with the new value until the next counter underflow.
The FLMC bit in MCCTL can be used to immediately update the count
register with the new value if an immediate load is desired.
If modulus mode is not enabled (MODMC=0), a write to this address will
clear the prescaler and will immediately update the counter register with
the value written to it and down-counts once to $0000
Timer Input
Capture Holding
Registers 0–3
(TC0H–TC3H)
Register offset: $0078–$007F
Bit 15
14
13
12
11
10
Read: Bit 15
14
13
12
11
10
Write:
Bit 7
6
5
4
3
2
Read: Bit 7
6
5
4
3
2
Write:
Reset:
0
0
0
0
0
0
= Reserved or unimplemented
Read: any time
Write: has no effect.
9
8
9
Bit 8
1
Bit 0
1
Bit 0
0
0
MOTOROLA
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1
407