MC9S12T64 Datasheet, PDF (45/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Instruction Set Overview
Table 4 Instruction Set Summary (Continued)
Source Form
LSL opr16aSame as ASL
LSL oprx0_xysppc
LSL oprx9,xysppc
LSL oprx16,xysppc
LSL [D,xysppc]
LSL [oprx16,xysppc]
LSLASame as ASLA
LSLBSame as ASLB
LSLDSame as ASLD
Operation
Address
Machine
Mode Coding (Hex)
Access Detail
Logical shift left M
C b7
0
b0
Logical shift left A
Logical shift left B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
78 hh ll
68 xb
68 xb ff
68 xb ee ff
68 xb
68 xb ee ff
48
58
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
Logical shift left D
INH
59
O
•••
•••
0
C b7 A b0 b7 B b0
LSR opr16a
LSR oprx0_xysppc
LSR oprx9,xysppc
LSR oprx16,xysppc
LSR [D,xysppc]
LSR [oprx16,xysppc]
LSRA
LSRB
LSRD
Logical shift right M
0
b7
b0 C
Logical shift right A
Logical shift right B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
74 hh ll
64 xb
64 xb ff
64 xb ee ff
64 xb
64 xb ee ff
44
54
Logical shift right D
INH
49
0
b7 A b0 b7 B b0 C
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
O
MAXA oprx0_xysppc
MAXA oprx9,xysppc
MAXA oprx16,xysppc
MAXA [D,xysppc]
MAXA [oprx16,xysppc]
Maximum in A; put larger of 2
IDX
unsigned 8-bit values in A
IDX1
MAX[(A), (M)]⇒A
IDX2
N, Z, V, C bits reflect result of internal [D,IDX]
compare [(A)–(M)]
[IDX2]
18 18 xb
18 18 xb ff
18 18 xb ee ff
18 18 xb
18 18 xb ee ff
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
MAXM oprx0_xysppc
MAXM oprx9,xysppc
MAXM oprx16,xysppc
MAXM [D,xysppc]
MAXM [oprx16,xysppc]
Maximum in M; put larger of 2
IDX
unsigned 8-bit values in M
IDX1
MAX[(A), (M)]⇒M
IDX2
N, Z, V, C bits reflect result of internal [D,IDX]
compare [(A)–(M)]
[IDX2]
18 1C xb
18 1C xb ff
18 1C xb ee ff
18 1C xb
18 1C xb ee ff
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
MEM
Determine grade of membership; Special 01
µ (grade)⇒M_Y; (X)+4⇒X; (Y)+1⇒Y
If (A)<P1 or (A)>P2, then µ=0; else µ=
MIN[((A)–P1)×S1, (P2–(A))×S2, $FF]
(A)=current crisp input value; X points
at 4 data bytes (P1, P2, S1, S2) of a
trapezoidal membership function; Y
points at fuzzy input (RAM location)
RRfOw
MINA oprx0_xysppc
MINA oprx9,xysppc
MINA oprx16,xysppc
MINA [D,xysppc]
MINA [oprx16,xysppc]
Minimum in A; put smaller of 2
IDX
unsigned 8-bit values in A
IDX1
MIN[(A), (M)]⇒A
IDX2
N, Z, V, C bits reflect result of internal [D,IDX]
compare [(A)–(M)]
[IDX2]
18 19 xb
18 19 xb ff
18 19 xb ee ff
18 19 xb
18 19 xb ee ff
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
MINM oprx0_xysppc
MINM oprx9,xysppc
MINM oprx16,xysppc
MINM [D,xysppc]
MINM [oprx16,xysppc]
Minimum in N; put smaller of two
IDX
unsigned 8-bit values in M
IDX1
MIN[(A), (M)]⇒M
IDX2
N, Z, V, C bits reflect result of internal [D,IDX]
compare [(A)–(M)]
[IDX2]
18 1D xb
18 1D xb ff
18 1D xb ee ff
18 1D xb
18 1D xb ee ff
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
MOVB #opr8, opr16a
MOVB #opr8i, oprx0_xysppc
MOVB opr16a, opr16a
MOVB opr16a, oprx0_xysppc
MOVB oprx0_xysppc, opr16a
MOVB oprx0_xysppc, oprx0_xysppc
Move byte
Memory-to-memory 8-bit byte-move
(M₁)⇒M₂
First operand specifies byte to move
IMM-EXT 18 0B ii hh ll OPwP
IMM-IDX 18 08 xb ii
OPwO
EXT-EXT 18 0C hh ll hh ll OrPwPO
EXT-IDX 18 09 xb hh ll OPrPw
IDX-EXT 18 0D xb hh ll OrPwP
IDX-IDX 18 0A xb xb
OrPwO
SXHINZVC
––––∆∆∆∆
––––∆∆∆∆
––––0∆∆∆
––––0∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––?–????
––––∆∆∆∆
––––∆∆∆∆
––––––––
MOTOROLA
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1
45