MC9S12T64 Datasheet, PDF (401/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
NOVWx — No Input Capture Overwrite
1 = The related capture register or holding register cannot be
written by an event unless they are empty (see IC Channels).
This will prevent the captured value to be overwritten until it is
read or latched in the holding register.
0 = The contents of the related capture register or holding register
can be overwritten when a new input capture or latch occurs.
NOTE: An IC register is empty when it has been read or latched into the holding
register.
NOTE: A holding register is empty when it has been read.
Input Control
System Control
Register (ICSYS)
Register offset: $006B
Bit 7
Read:
Write:
SH37
Reset:
0
6
5
4
3
2
1
Bit 0
SH26
SH15
SH04
TFMOD
PACMX
BUFEN
LATQ
0
0
0
0
0
0
0
Read: any time
Write: May be written once in normal modes. Writes are always
permitted when special modes.
SHxy — Share Input action of Input Capture Channels x and y
1 = The channel input ‘x’ causes the same action on the channel
‘y’. The port pin ‘x’ and the corresponding edge detector is
used to be active on the channel ‘y’.
0 = Normal operation
TFMOD — Timer Flag-setting Mode
Use of the TFMOD bit in the ICSYS register in conjunction with the
use of the ICOVW register allows a timer interrupt to be generated
after capturing two values in the capture and holding registers instead
of generating an interrupt for every capture.
MOTOROLA
Enhanced Capture Timer (ECT)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1
401