MC9S12T64 Datasheet, PDF (281/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Register Descriptions
Read: anytime.
Write: anytime except if PLLSEL = 1.
NOTE: Write to this register initializes the lock detector bit and the track detector
bit.
CRG Reference
Divider Register
(REFDV)
The REFDV register provides a finer granularity for the PLL multiplier
steps. The count in the reference divider divides OSCCLK frequency by
REFDV+1.
Address Offset: $0035
Bit 7
Read:
0
Write:
Reset:
0
6
5
4
0
0
0
0
0
0
= Unimplemented or reserved
3
REFDV3
0
2
REFDV2
0
1
REFDV1
0
0
REFDV0
0
Read: anytime.
Write: anytime except when PLLSEL = 1.
NOTE: Write to this register initializes the lock detector bit and the track detector
bit.
CRG Flags Register This register provides CRG status bits and flags.
(CRGFLG)
Address Offset: $0037
Bit 7
6
5
4
3
2
1
0
Read:
0
RTIF PORLVDRF
Write:
Reset:
0
(1)
0
LOCK
TRACK
SCM
LOCKIF
SCMIF
0
0
0
0
0
= Unimplemented or reserved
1. PORLVDRF set to 1 when a power on reset or low-voltage detection reset occurs. Unaffected by non-POR resets.
MOTOROLA
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1
281