MC9S12T64 Datasheet, PDF (296/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Acquisition and
Tracking Modes
output the REFERENCE clock. The VCO output clock, (PLLCLK) is fed
back through the programmable loop divider and is divided in a range of
2 to 128 in increments of [2 x (SYNR +1)] to output the FEEDBACK
clock. See Figure 46.
The phase detector then compares the FEEDBACK clock, with the
REFERENCE clock. Correction pulses are generated based on the
phase difference between the two signals. The loop filter then slightly
alters the DC voltage on the external filter capacitor connected to XFC
pin, based on the width and direction of the correction pulse. The filter
can make fast or slow corrections depending on its mode, as described
in the next subsection. The values of the external filter network and the
reference frequency determine the speed of the corrections and the
stability of the PLL.
The lock detector compares the frequencies of the FEEDBACK clock,
and the REFERENCE clock. Therefore, the speed of the lock detector is
directly proportional to the final reference frequency. The circuit
determines the mode of the PLL and the lock condition based on this
comparison¹.
The PLL filter can be manually or automatically configured into one of
two possible operating modes:
• Acquisition mode
In acquisition mode, the filter can make large frequency
corrections to the VCO. This mode is used at PLL start-up or when
the PLL has suffered a severe noise hit and the VCO frequency is
far off the desired frequency. When in acquisition mode, the
TRACK status bit is cleared in the CRGFLG register.
• Tracking mode
1. See Table 118 in page 582 for actual values of the parameters men-
tioned in this section.
MC9S12T64Revision 1.1.1
296
Clocks and Reset Generator (CRG)
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