MC9S12T64 Datasheet, PDF (301/608 Pages) Motorola, Inc – Specification

Clock Quality
Checker
Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Functional Description
The clock monitor performs a coarse check on the incoming clock signal.
The clock quality checker provides a more accurate check in addition to
the clock monitor. The clock quality checker expects a valid OSCLK to
have 4096 rising OSCCLK edges within a time window of 50 000 VCO
clock cycles¹ (See Figure 49). This time window is called check window.
If the requested number of 4096 rising OSCCLK edges occur within the
check window, the quality of the OSCCLK is considered to be valid and
the OSCCLK becomes the source for systems and core clocks. Note
that if 4096 OSCCLK edges are counted within the check window, the
check window is immediately terminated.
VCO Clock
OSCCLK
.
12
Check window
3
49999 50000
12345
4096
4095
OSCCLK OK
Figure 49 Check Window definition
MOTOROLA
A clock quality check is triggered by any of the following events:
• Power-on Reset (POR)
• Low Voltage Detection Reset (LVDR)
• Wake-up from Full Stop Mode (Exit_Full_Stop)
• Clock Monitor fail indication (CM_Fail)
1. VCO clock cycles are generated by the PLL when running at minimum frequency f_SCM.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
301
For More Information On This Product,
Go to: www.freescale.com