MC9S12T64 Datasheet, PDF (496/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
1 = ATD Interrupt will be requested whenever ASCIF=1 is set.
0 = ATD Sequence Complete interrupt requests are disabled.
NOTE: There is an errata information about the ASCIF flag. See MC9S12 Errata
Sheet for details.
ASCIF — ATD Sequence Complete Interrupt Flag
If ASCIE=1 the ASCIF flag equals the SCF flag (see register
ATDSTAT0 - page 505), else ASCIF reads zero. Writes have no
effect.
1 = ATD sequence complete interrupt pending
0 = No ATD interrupt occurred
ATD Control
Register 3
(ATDCTL3)
Address Offset: $0083
Bit 7
Read:
0
Write:
Reset:
0
This register controls the conversion sequence length, FIFO for results
registers and behavior in Freeze Mode. Writes to this register will abort
current conversion sequence but will not start a new sequence.
6
5
4
3
2
1
Bit 0
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
0
1
0
0
0
0
0
Unimplemented or Reserved
S8C/S4C/S2C/S1C — Conversion Sequence Length
These bits control the number of conversions per sequence. Table 87
shows all combinations. At reset, S4C is set to 1 (sequence length is
4). This is to maintain software continuity to HC12 family.
Table 87 Conversion Sequence Length Coding.
S8C S4C
0
0
0
0
0
0
0
0
0
1
S2C S1C
0
0
0
1
1
0
1
1
0
0
Number of Conversions per
Sequence
8
1
2
3
4
MC9S12T64Revision 1.1.1
496
Analog to Digital Converter (ATD)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA