MC9S12T64 Datasheet, PDF (289/608 Pages) Motorola, Inc – Specification

Address Offset: $003B
Bit 7
Reset:
0
Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Read: anytime
Write: anytime.
NOTE: A write to this register will initialize the RTI counter.
RTR[6:4] — Real Time Interrupt Prescale Rate Select Bits
These bits select the prescale rate for the RTI. See Table 51.
RTR[3:0] — Real Time Interrupt Modulus Counter Select
These bits select the modulus counter target value to provide
additional granularity. See Table 51.
Table 51 shows all possible divide values selectable by the RTICTL
register. The source clock for the RTI is OSCCLK.
RTR[3:0]
0 (÷1)
1 (÷2)
2 (÷3)
3 (÷4)
4 (÷5)
5 (÷6)
6 (÷7)
7 (÷8)
8 (÷9)
9 (÷10)
10 (÷11)
11 (÷12)
12 (÷13)
Table 51 RTI Frequency Divide Rates
000
(OFF)
OFF ⁽¹⁾⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
OFF ⁽²⁾
001
(2¹⁰)
2¹⁰
2x2¹⁰
3x2¹⁰
4x2¹⁰
5x2¹⁰
6x2¹⁰
7x2¹⁰
8x2¹⁰
9x2¹⁰
10x2¹⁰
11x2¹⁰
12x2¹⁰
13x2¹⁰
010
(2¹¹)
2¹¹
2x2¹¹
3x2¹¹
4x2¹¹
5x2¹¹
6x2¹¹
7x2¹¹
8x2¹¹
9x2¹¹
10x2¹¹
11x2¹¹
12x2¹¹
13x2¹¹
RTR[6:4] =
011
(2¹²)
2¹²
2x2¹²
3x2¹²
4x2¹²
5x2¹²
6x2¹²
7x2¹²
8x2¹²
9x2¹²
10x2¹²
11x2¹²
12x2¹²
13x2¹²
100
(2¹³)
2¹³
2x2¹³
3x2¹³
4x2¹³
5x2¹³
6x2¹³
7x2¹³
8x2¹³
9x2¹³
10x2¹³
11x2¹³
12x2¹³
13x2¹³
101
(2¹⁴)
2¹⁴
2x2¹⁴
3x2¹⁴
4x2¹⁴
5x2¹⁴
6x2¹⁴
7x2¹⁴
8x2¹⁴
9x2¹⁴
10x2¹⁴
11x2¹⁴
12x2¹⁴
13x2¹⁴
110
(2¹⁵)
2¹⁵
2x2¹⁵
3x2¹⁵
4x2¹⁵
5x2¹⁵
6x2¹⁵
7x2¹⁵
8x2¹⁵
9x2¹⁵
10x2¹⁵
11x2¹⁵
12x2¹⁵
13x2¹⁵
111
(2¹⁶)
2¹⁶
2x2¹⁶
3x2¹⁶
4x2¹⁶
5x2¹⁶
6x2¹⁶
7x2¹⁶
8x2¹⁶
9x2¹⁶
10x2¹⁶
11x2¹⁶
12x2¹⁶
13x2¹⁶
MOTOROLA
Clocks and Reset Generator (CRG)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1
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