MC9S12T64 Datasheet, PDF (305/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Operation Modes
Operation Modes
Normal Mode
The CRG module behaves as described within this specification in all
normal modes.
Self Clock Mode
The VCO has a minimum operating frequency, f_SCM. If the external clock
frequency is not available due to a failure or due to long crystal start-up
time, the Bus Clock and the Core Clock are derived from the VCO
running at minimum operating frequency; this mode of operation is
called Self Clock Mode. This requires CME=1 and SCME=1. If the MCU
was clocked by the PLL clock prior to entering Self Clock Mode, the
PLLSEL bit will be cleared. If the external clock signal has stabilized
again, the CRG will automatically select OSCCLK to be the system clock
and return to normal mode. See Clock Quality Checker in page 301 for
more information on entering and leaving Self Clock Mode.
NOTE: In order to detect a potential clock loss the CME bit should be always
enabled (CME=1)!
If CME bit is disabled and the MCU is configured to run on PLL clock
(PLLCLK), a loss of external clock (OSCCLK) will not be detected and
will cause the system clock to drift towards the VCO’s minimum
frequency f_SCM. As soon as the external clock is available again the
system clock ramps up to its PLL target frequency. If the MCU is running
on external clock any loss of clock will cause the system to go static.
Low Power Options
This section summarizes the low power options available in the CRG.
Run Mode
The RTI can be stopped by setting the associated rate select bits to zero.
The COP can be stopped by setting the associated rate select bits to
zero.
MOTOROLA
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1
305