MC9S12T64 Datasheet, PDF (47/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Instruction Set Overview
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Machine
Mode Coding (Hex)
Access Detail S X H I N Z V C
PULX
Pull X
INH
30
UfO
(M_SP:M_SP+1)⇒X_H:X_L; (SP)+2⇒SP
––––––––
PULY
Pull Y
INH
31
UfO
(M_SP:M_SP+1)⇒Y_H:Y_L; (SP)+2⇒SP
––––––––
REV
Rule evaluation, unweighted; find Special 18 3A
smallest rule input; store to rule
outputs unless fuzzy output is larger
Orf(t^tx)O*
ff+Orft^**
––?–??∆?
*The t^tx loop is executed once for each element in the rule list. The ^ denotes a check for pending interrupt requests.
**These are additional cycles caused by an interrupt: ff is the exit sequence and Orft^ is the re-entry sequence.
REVW
Rule evaluation, weighted; rule
weights optional; find smallest rule
input; store to rule outputs unless
fuzzy output is larger
Special 18 3B
ORf(t^Tx)O*
or
ORf(r^ffRf)O**
ffff+ORft^***
ffff+ORfr^****
––?–??∆ !
*With weighting not enabled, the t^Tx loop is executed once for each element in the rule list. The ^ denotes a check for pending interrupt requests.
**With weighting enabled, the t^Tx loop is replaced by r^ffRf.
***Additional cycles caused by an interrupt when weighting is not enabled: ffff is the exit sequence and ORft^ is the re-entry sequence.
**** Additional cycles caused by an interrupt when weighting is enabled: ffff is the exit sequence and ORfr^ is the re-entry sequence.
ROL opr16a
ROL oprx0_xysppc
ROL oprx9,xysppc
ROL oprx16,xysppc
ROL [D,xysppc]
ROL [oprx16,xysppc]
ROLA
ROLB
Rotate left M
C b7
b0
Rotate left A
Rotate left B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
75 hh ll
65 xb
65 xb ff
65 xb ee ff
65 xb
65 xb ee ff
45
55
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
––––∆∆∆∆
ROR opr16a
ROR oprx0_xysppc
ROR oprx9,xysppc
ROR oprx16,xysppc
ROR [D,xysppc]
ROR [oprx16,xysppc]
RORA
RORB
Rotate right M
b0
b7 C
Rotate right A
Rotate right B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
76 hh ll
66 xb
66 xb ff
66 xb ee ff
66 xb
66 xb ee ff
46
56
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
––––∆∆∆∆
RTC
Return from call; (M_SP)⇒PPAGE
INH
0A
(SP)+1⇒SP;
(M_SP:M_SP+1)⇒PC_H:PC_L
(SP)+2⇒SP
uUnfPPP
––––––––
RTI
Return from interrupt
(M_SP)⇒CCR; (SP)+1⇒SP
INH
0B
uUUUUPPP
or
∆⇓∆∆∆∆∆∆
(M_SP:M_SP+1)⇒B:A;(SP)+2⇒SP
uUUUUfVfPPP*
(M_SP:M_SP+1)⇒X_H:X_L;(SP)+4⇒SP
(M_SP:M_SP+1)⇒PC_H:PC_L;(SP)+2⇒SP
(M_SP:M_SP+1)⇒Y_H:Y_L;(SP)+4⇒SP
*RTI takes 11 cycles if an interrupt is pending.
RTS
Return from subroutine
(M_SP:M_SP+1)⇒PC_H:PC_L;
(SP)+2⇒SP
INH
3D
UfPPP
––––––––
SBA
Subtract B from A; (A)–(B)⇒A
INH
18 16
OO
––––∆∆∆∆
MOTOROLA
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1
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