MC9S12T64 Datasheet, PDF (536/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Firmware
commands
For firmware read commands, the external host must wait 32 target
clock cycles after sending the command opcode before attempting to
obtain the read data. If the access is external with a narrow bus access
(+1 cycle) and / or a stretch (+1, 2 or 3 cycles), up to an additional 7
cycles could be needed if both occur (39 target clock cycles total). This
allows enough time for the requested data to be made available in the
BDM shift register, ready to be shifted out. For firmware write
commands, the external host must wait 32 target clock cycles after
sending the data to be written, before attempting to send a new
command. This is to avoid disturbing the BDM shift register before the
write has been completed.
The external host should wait 64 target clock cycles after a TRACE1 or
GO command before starting any new serial command. This is to allow
the CPU to exit gracefully from the standard BDM firmware lookup table
and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM
firmware lookup table.
Figure 102 represents the BDM command structure in single wire mode.
The command blocks illustrate a series of eight bit times starting with a
falling edge. The bar across the top of the blocks indicates that the
BKGD line idles in the high state. The minimum time for an 8-bit
command is 8 × 16 target clock cycles.
MC9S12T64Revision 1.1.1
536
Fast Background Debug Module (FBDM)
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