MC9S12T64 Datasheet, PDF (164/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
signals are available on two multifunctional device pins. During reset, the
pins are mode-select inputs MODA and MODB. After reset, information
on the pins does not become valid until an instruction reaches stage two
of the queue.
To reconstruct the queue, the information carried by the status signals
must be captured externally. In general, data-movement and
execution-start information are considered to be distinct two-bit values,
with the low bit on IPIPE0 and the high bit on IPIPE1. Data-movement
information is available when E clock is high or on falling edges of the E
clock; execution-start information is available when E clock is low or on
rising edges of the E clock, as shown in Figure 18. Data-movement
information refers to data on the bus. Execution-start information is
delayed one bus cycle to guarantee the indicated opcode is in stage
three. Table 31 summarizes the information encoded on the IPIPE[1:0]
pins.
CPU CLOCK T4
T2
T4
T2
T4
T2
E CLOCK
EX
DM
EX
DM
EX
DM
PIPE[1:0]
00
10
10
00
11
10
NONE
ALD A
SEV B
NONE
SOD C
ALD
DATA[15:0]
PROGRAM DATA
OPERAND OR FREE CYCLE
PROGRAM DATA
STAGE THREE
B
C
STAGE TWO
STAGE ONE
A
ALD — Advance and load data
SEV — Start even instruction
SOD — Start odd instruction
A
Figure 18 Queue Status Signal Timing
Data movement status is valid when the E clock is high and is
represented by two states:
• No movement — There is no data shifting in the queue.
MC9S12T64Revision 1.1.1
164
Multiplexed External Bus Interface (MEBI)
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