MC9S12T64 Datasheet, PDF (394/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
PAIF — Pulse Accumulator Input edge Flag
Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation
mode the trailing edge of the gate signal at the PT7 input pin triggers
PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set. Any
access to the PACN3, PACN2 registers will clear all the flags in this
register when TFFCA bit in register TSCR1 is set.
Pulse
Accumulators
Count Registers
(PACN3, PACN2)
Register offset: $0062–$0063
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIt 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
Read or write any time.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form
the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1
in PACTL) the PACN3 and PACN2 registers contents are respectively
the high and low byte of the PACA.
When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in
PAFLG is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
NOTE:
The input capture edge circuits of 8-bit pulse accumulators are
configured with control bits EDGnA and EDGnB in the TCTL4 register
(see page 386).
MC9S12T64Revision 1.1.1
394
Enhanced Capture Timer (ECT)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA