MC9S12T64 Datasheet, PDF (372/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Features
• 16-Bit Buffer Register for four Input Capture (IC) channels.
• Four 8-Bit Pulse Accumulators with 8-bit buffer registers
associated with the four buffered IC channels. Configurable also
as two 16-Bit Pulse Accumulators.
• 16-Bit Modulus Down-Counter with 4-bit Prescaler.
• Four user selectable Delay Counters for input noise immunity
increase.
• Support for only 16-bit access on the IP bus.
Modes of Operation
STOP:
FREEZE:
WAIT:
NORMAL:
Timer and modulus counter are off since clocks are
stopped.
The ECT module enters freeze mode when background
debug mode (BDM) is active. In freeze mode, timer and
modulus counter keep on running, unless TSFRZ in
TSCR1 (see page 382) is set to one.
Counters keep on running, unless TSWAI in TSCR1 is set
to one.
Timer and modulus counter keep on running, unless TEN
in TSCR1 and MCEN in MCCTL (see page 396),
respectively, are cleared.
Abbreviations
Following abbreviations are used in the document.
PACLK – 16-bit pulse accumulator A (PACA) clock
MC9S12T64Revision 1.1.1
372
Enhanced Capture Timer (ECT)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA