MC9S12T64 Datasheet, PDF (175/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Resets and Interrupts
Register Descriptions
Register Descriptions
Interrupt Control
and Priority
Register
IRQCR — IRQ Control Register
Address Offset: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
IRQE
IRQEN
Write:
Reset: 0
1
0
0
0
0
0
0
= Unimplemented or reserved
Read: refer to individual bit descriptions
Write: refer to individual bit descriptions
IRQE — IRQ Select Edge Sensitive Only
Special modes: read or write anytime
Normal & Emulation modes: read anytime, write once
1 = IRQ configured to respond only to falling edges. Falling edges
on the IRQ pin will be detected anytime IRQE = 1 and will be
cleared only upon a reset or the servicing of the IRQ interrupt.
0 = IRQ configured for low-level recognition.
IRQEN — External IRQ Enable
Normal, Emulation, and Special modes: read or write anytime
1 = External IRQ pin is connected to interrupt logic.
0 = External IRQ pin is disconnected from interrupt logic.
NOTE: When IRQEN=0, the edge detect latch is disabled.
MOTOROLA
Resets and Interrupts
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MC9S12T64Revision 1.1.1
175