MC9S12T64 Datasheet, PDF (494/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
Register Descriptions
The following subsections describe the bit-level arrangement and
functionality of each register.
ATD Control
Register 2
(ATDCTL2)
This register controls power down, interrupt and external trigger. Writes
to this register will abort current conversion sequence but will not start a
new sequence.
Address Offset: $0082
Bit 15
Read:
ADPU
Write:
Reset:
0
14
AFFC
13
AWAI
12
ETRIGLE
11
ETRIGP
10
ETRIGE
9
ASCIE
Bit 8
ASCIF
0
0
0
0
0
0
0
READ: anytime
WRITE: anytime
(except for Bit 8 – ASCIF, READ: any time, WRITE: not allowed)
ADPU — ATD Power Down
This bit provides on/off control over the ATD module block allowing
reduced MCU power consumption. Because analog electronic is
turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
1 = Normal ATD functionality
0 = Power down ATD
AFFC — ATD Fast Flag Clear All
1 = Changes all ATD conversion complete flags to a fast clear
sequence. Any access to a result register will cause the
associate CCF flag to clear automatically.
0 = ATD flag clearing operates normally (read the status register
ATDSTAT1 before reading the result register to clear the
associate CCF flag).
AWAI — ATD Power Down in Wait Mode
MC9S12T64Revision 1.1.1
494
Analog to Digital Converter (ATD)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA