MC9S12T64 Datasheet, PDF (403/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set
will produce latching of input capture and pulse accumulators
registers into their holding registers.
1 = Latch Mode is enabled. Latching function occurs when
modulus down-counter reaches zero or a zero is written into
the count register MCCNT (see Buffered IC Channels).
With a latching event the contents of IC registers and 8-bit
pulse accumulators are transferred to their holding registers.
8-bit pulse accumulators are cleared.
0 = Queue Mode of Input Capture is enabled.
The main timer value is memorized in the IC register by a valid
input pin transition.
With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register
memorizes the new timer value.
MOTOROLA
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1
403