MC9S12T64 Datasheet, PDF (318/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Reset Description
General
This section describes how to reset the CRG and how the CRG itself
controls the reset of the MCU. It explains all special reset requirements.
Since the reset generator for the MCU is part of the CRG this section
also describes all automatic actions that occur during or as a result of
individual reset conditions. The reset values of registers and signals are
provided in Register Descriptions in page 280. All reset sources are
listed in Table 56. Refer to MCU specification for related vector
addresses and priorities.
Table 56 Reset Summary
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
Reset Source
Power-on Reset
LVD Reset
External Reset
Clock Monitor Reset
COP Watchdog Reset
Local Enable
None
LVDCR
(LVDE=1 and LVDRE=1)
None
PLLCTL (CME=1, SCME=0)
COPCTL (CR[2:0] nonzero)
Description of
Reset Operation
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET pin (External Reset).
• Power-on is detected. (Power-on Reset - POR)
• Low voltage condition is detected. (Low Voltage Detection Reset
LVDR)
• COP watchdog times out. (COP reset - COPR)
• Clock monitor failure is detected and Self-Clock Mode was
disabled (SCME=0). (Clock Monitor Reset - CMR)
Upon detection of any reset event, an internal circuit drives the RESET
pin low for 128 SYSCLK cycles (see Figure 55). Since entry into reset is
asynchronous it does not require a running SYSCLK. However, the
internal reset circuit of the CRG cannot sequence out of current reset
condition without a running SYSCLK. The number of 128 SYSCLK
cycles might be increased by n=3 to 6 additional SYSCLK cycles
MC9S12T64Revision 1.1.1
318
Clocks and Reset Generator (CRG)
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