MC9S12T64 Datasheet, PDF (479/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Functional Description
Transfer
Begin
End
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
t_L
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
t_L = Minimum leading time before the first SCK edge
t_T = Minimum trailing time after the last SCK edge
t_I = Minimum idling time between transfers (minimum SS high time)
t_L, t_T, and t_I are guaranteed for the master mode and required for the slave mode.
Bit 1
Bit 6
t_T t_I t_L
LSB Minimum 1/2 SCK
MSB
for t_T, t_l, t_L
Figure 95 SPI Clock Format 1 (CPHA = 1)
The SS line can remain active low between successive transfers (can be
tied low at all times). This format is sometimes preferred in systems
having a single fixed master and a single slave that drive the MISO data
line.
The SPI interrupt request flag (SPIF) is common to both the master and
slave modes. SPIF gets set after the last SCK edge in a data transfer
operation to indicate that the transfer is complete though transfer is
actually complete half SCK cycle later.
SPI Baud Rate
Generation
MOTOROLA
Baud rate generation consists of a series of divider stages. Six bits in the
SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and
SPR0) determine the divisor to the bus clock which results in the SPI
baud rate.
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1
479