MC68HC908EY16 Datasheet, PDF (96/278 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
8.6.4 Oscillator Enable In Stop (OSCENINSTOP)
Oscillator enable in stop (OSCENINSTOP), when set, will enable the ICG to continue to generate clocks
(either CGMXCLK, CGMOUT, or TBMCLK) in stop mode. This function is used to keep the timebase
running while the rest of the microcontroller stops. When OSCENINSTOP is clear, all clock generation
will cease and CGMXCLK, CGMOUT, and TBMCLK will be forced low during stop mode.
The default state for this option is clear.
8.7 Input/Output (I/O) Registers
The ICG contains five registers. These registers are:
1. ICG control register, ICGCR
2. ICG multiplier register, ICGMR
3. ICG trim register, ICGTR
4. ICG DCO divider control register, ICGDVR
5. ICG DCO stage control register, ICGDSR
Several of the bits in these registers have interaction where the state of one bit may force another bit to
a particular state or prevent another bit from being set or cleared. A summary of this interaction is shown
in Table 8-4.
Table 8-4. ICG Module Register Bit Interaction Summary
Condition
Register Bit Results for Given Condition
CMIE CMF CMON CS ICGON ICGS ECQON ECQ N[6:0] TRIM[7:0] DDIV[3:0] DSTQ[7:0]
Reset
00
00 1
0
0
0 $15
$80
—
—
OSCENINSTOP = 0,
STOP = 1
0
0
0 ——
0
—
0—
—
—
—
EXTCLKEN = 0
00
00 1
—
0
0—
—
uw
uw
CMF = 1
— (1) 1 — 1
—
1
— uw
uw
uw
uw
CMON = 0
0 0 (0) — —
—
—
——
—
—
—
CMON = 1
— — (1) — 1
—
1
— uw
uw
uw
uw
CS = 0
— — — (0) 1
—
—
——
—
uw
uw
CS = 1
— — — (1) — —
1
——
—
—
—
ICGON = 0
00
0 1 (0)
0
1
——
—
—
—
ICGON = 1
— — — — (1) —
—
——
—
uw
uw
ICGS = 0
us — us uc —
(0)
—
——
—
—
—
ECGON = 0
00
00 1
— (0)
0—
—
uw
uw
ECGS = 0
us — us us —
—
— (0) —
—
—
—
IOFF = 1
— 1* (1) 1 (1)
0
(1) — uw
uw
uw
uw
EOFF = 1
— 1* (1) 0 (1) —
(1)
0 uw
uw
uw
uw
N = written
(0) (0) (0) — — 0*
—
——
—
—
—
TRIM = written
(0) (0) (0) — — 0*
—
——
—
—
—
—
0, 1
0*, 1*
(0), (1)
us, uc, uw
Register bit is unaffected by the given condition.
Register bit is forced clear or set (respectively) in the given condition.
Register bit is temporarily forced clear or set (respectively) in the given condition.
Register bit must be clear or set (respectively) for the given condition to occur.
Register bit cannot be set, cleared, or written (respectively) in the given condition.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
96
Freescale Semiconductor