MC68HC908EY16 Datasheet, PDF (62/278 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly (COP) Module
an overflow occurs prevents a COP reset by clearing the COP counter and stages 4–12 of the SIM
counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held at V_TST. During the break state,
V_TST on the RST pin disables the COP.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
6.3.2 STOP Instruction
The STOP instruction signal clears the COP prescaler.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 6.4 COP Control Register) clears the COP
counter and clears stages 12 through 4 of the COP prescaler. Reading the COP control register returns
the reset vector.
6.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
6.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
6.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
6.3.7 COPD
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 5 Configuration Registers (CONFIG1 and CONFIG2).
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
62
Freescale Semiconductor