MC68HC908EY16 Datasheet, PDF (269/278 Pages) Motorola, Inc – Microcontrollers

Revision History
Changes from Rev 9.0 published in August 2005 to Rev 10 published in October 2005
Section
Configuration
Registers (CONFIG1
and CONFIG2)
System Integration
Module (SIM)
Timebase Module
(TBM)
Page (in Rev 10)
57
159
189
Description of change
Figure 5-1. Configuration Register 2 (CONFIG2) — Corrected name for bit 6
to ESCIBDSRC.
14.3.2.5 Forced Monitor Mode Entry Reset (MENRST) — Corrected erased
value from $00 to $FF.
Figure 16-1. Timebase Block Diagram — Corrected label from
TBMCLKSEL to TMBCLKSEL.
Changes from Rev 8.0 published in July 2005 to Rev 9 published in August 2005
Section
Throughout
Memory
Analog-to-Digital
Converter (ADC)
Module
Computer Operating
Properly (COP)
Module
Keyboard Interrupt
(KBD) Module
Low-Voltage Inhibit
(LVI) Module
Input/Output (I/O)
Ports (PORTS)
Enhanced Serial
Communications
Interface (ESCI)
Module
Page (in Rev 9)
N/A
32
53
Description of change
Updated to meet Freescale identity guidelines.
Changed ADRH register bit names at address location $003D from ADCH9
and ADCH8 to AD9 and AD8 respectively.
Table 3-2. ADC Clock Divide Ratio — Changed last table entry under ADC
Clock Rate from ADC input clock ÷ 6 to ADC input clock ÷ 16.
63
6.6 Monitor Mode — changed V_DD = V_TST is present to V_TST is present.
110
10.7.2 Keyboard Interrupt Enable Register — In bit definition changed PDx
to KBDx.
112
11.3.1 Polled LVI Operation — Changed LVIRSTD bit must be at 0 to enable
LVI resets to LVIRSTD bit must be at 1 to disable LVI resets
11.5.2 Stop Mode — Changed LVIPWRD bit in the configuration register
113
programmed to 0 to LVIPWRD bit in the configuration register programmed
to 1
117
Figure 12-4. Port B Data Register (PTB) — Changed ATD7–ATD0 to
AD7–AD0 in both the bit descriptions and alternative function blocks.
142
13.8.3 ESCI Control Register 3 — In the bit description for PEIE, changed
ESCI receiver CPU interrupt request to ESCI error CPU interrupt request
143
13.8.4 ESCI Status Register 1 — In the bit description for IDLE, changed
ESCI error CPU interrupt request to ESCI receiver CPU interrupt request.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
269