MC68HC908EY16 Datasheet, PDF (177/278 Pages) Motorola, Inc – Microcontrollers

Error Conditions
15.6.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data register still has unread data
from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. (See
Figure 15-4 and Figure 15-5.) If an overflow occurs, the data being received is not transferred to the
receive data register so that the unread data can still be read. Therefore, an overflow error always
indicates the loss of data.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR)
is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 15-9.) It
is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow
condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is
enabled to generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 15-7 shows how it is possible to miss an overflow.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ SPSCR
2
5
READ SPDR
3
7
1 BYTE 1 SETS SPRF BIT.
5 CPU READS SPSCRW WITH SPRF BIT SET AND OVRF BIT CLEAR.
2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3 CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT.
7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT.
4 BYTE 2 SETS SPRF BIT.
8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 15-7. Missed Read of Overflow Condition
The first part of Figure 15-7 shows how to read the SPSCR and SPDR to clear the SPRF without
problems. However, as illustrated by the second transmission example, the OVRF flag can be set in
between the time that SPSCR and SPDR are read.
In this case, an overflow can be easily missed. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of the SPSCR after the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions will complete with an SPRF interrupt. Figure 15-8 illustrates this process. Generally, to
avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit (SPSCR).
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
177