MC68HC908EY16 Datasheet, PDF (213/278 Pages) Motorola, Inc – Microcontrollers

Functional Description
18.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTB6/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and
channel 1. The output compare value in the TIMB channel 0 registers initially controls the output on the
PTB6/TBCH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to
synchronously control the output after the TIMB overflows. At each subsequent overflow, the TIMB
channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors
the buffered output compare function, and TIMB channel 1 status and control register (TBSC1) is unused.
While the MS0B bit is set, the channel 1 pin, PTB7/TBCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
18.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM
signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 18-3 shows, the output compare value in the TIMB channel registers determines the pulse
width of the PWM signal. The time between overflow and output compare is the pulse width. Program the
TIMB to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the
TIMB to set the pin if the state of the PWM pulse is logic 0.
OVERFLOW
PERIOD
PTBx/TCHx
PULSE
WIDTH
OVERFLOW
OVERFLOW
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 18-3. PWM Period and Pulse Width
OUTPUT
COMPARE
The value in the TIMB counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000 (see 18.8.1 TIMB Status and Control Register).
The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50%.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
213