MC68HC908EY16 Datasheet, PDF (217/278 Pages) Motorola, Inc – Microcontrollers

18.8 I/O Registers
These I/O registers control and monitor TIMB operation:
• TIMB status and control register, TBSC
• TIMB control registers, TBCNTH–TBCNTL
• TIMB counter modulo registers, TBMODH–TBMODL
• TIMB channel status and control registers, TBSC0 and TBSC1
• TIMB channel registers, TBCH0H–TBCH0L and TBCH1H–TBCH1L
18.8.1 TIMB Status and Control Register
The TIMB status and control register:
• Enables TIMB overflow interrupts
• Flags TIMB overflows
• Stops the TIMB counter
• Resets the TIMB counter
• Prescales the TIMB counter clock
I/O Registers
Address: $002B
Bit 7
6
5
4
3
Read: TOF
0
TOIE TSTOP
R
Write: 0
TRST
2
1
Bit 0
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
R
= Reserved
Figure 18-4. TIMB Status and Control Register (TBSC)
TOF — TIMB Overflow Flag Bit
This read/write flag is set when the TIMB counter reaches the modulo value programmed in the TIMB
counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set
and then writing a 0 to TOF. If another TIMB overflow occurs before the clearing sequence is complete,
then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
1 = TIMB counter has reached modulo value
0 = TIMB counter has not reached modulo value
TOIE — TIMB Overflow Interrupt Enable Bit
This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
217