MC68HC908EY16 Datasheet, PDF (189/278 Pages) Motorola, Inc – Microcontrollers

Chapter 16
Timebase Module (TBM)
16.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user
selectable rates using a counter clocked by either the internal or external clock sources. This TBM version
uses 15 divider stages, eight of which are user selectable.
NOTE
The TBM on this device differs from that of the MC68HC908KX8 in that it
has an additional divide-by-128 at the front end of the divider chain.
For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer
Reference Manual, Freescale order number TIM08RM/AD.
16.2 Features
Features of the TBM module include:
• Software configurable periodic interrupts with divide-by-1024, 2048, 4096, 8192, 16384, 262144,
1048576, and 4194304 taps of the selected clock source
• Configurable for operation during stop mode to allow periodic wake up from stop
16.3 Functional Description
This module can generate a periodic interrupt by dividing the clock source supplied from the internal clock
generator module, TBMCLK. Note that this clock source is the external clock ECLK when the ECGON bit
in the ICG control register (ICGCR) is set. Otherwise, TBMCLK is driven at the internally generated clock
frequency (ICLK). In other words, if the external clock is enabled it will be used as the TBMCLK, even if
the MCU bus clock is based on the internal clock.
The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 16-1, starts
counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2–TBR0, the
TBIF bit gets set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared
by writing a 1 to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the
interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact
period.
The timebase module may remain active after execution of the STOP instruction if the internal clock
generator has been enabled to operate during stop mode through the OSCENINSTOP bit in the
configuration register. The timebase module can be used in this mode to generate a periodic wakeup from
stop mode.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
189