MC68HC908EY16 Datasheet, PDF (117/278 Pages) Motorola, Inc – Microcontrollers

Port B
12.3 Port B
Port B is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter (ADC)
and some pin functions with TIMB.
Port B is designed so that the ADC function will take priority over the timer functionality on PTB6 and
PTB7. If the ADC is selected for a conversion on a previously enabled timer pin, the port pin will be
connected to the ADC and disconnected from the timer. If both the timer input capture and ADC functions
are being used on the same port pin, it is recommended that the timer channel be diabled before the pin
is enabled as an ADC input to avoid glitches. If both the timer output compare (or PWM) and ADC
functions are being used on the same port pin, it is recommended that the timer channel be disabled
before the pin is enabled as an ADC input.
12.3.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B pins.
Address:
Read:
Write:
Reset:
Alternative Function:
$0001
Bit 7
PTB7
AD7
6
PTB6
AD6
5
PTB5
AD5
4
3
PTB4
PTB3
Unaffected by reset
AD4
AD3
2
PTB2
AD2
1
PTB1
AD1
Bit 0
PTB0
AD0
Alternative Function: TBCH1 TBCH0
Figure 12-4. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
AD[7:0] — ADC Channels
PTB7–PTB0 are eight ADC channels. The ADC channel select bits, CH[4:0], determine whether the
PTB7–PTB0 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a
read of this corresponding bit in the port B data register occurs, the data will be a 0 if the data direction
for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch (see
Chapter 3 Analog-to-Digital Converter (ADC) Module). DDRB does not affect the data direction of
port B pins that are being used by the ADC. However, the DDRB bits always determine whether
reading port B returns to the states of the latches or 0.
TBCH[1:0] — Timer Channel I/O Bits
The PTB7/TBCH1–PTB6/TBCH0 pins are the TIMB input capture/output compare pins. The
edge/level select bits, ELSxB–ELSxA, determine whether the PTB7/TBCH1–PTB6/TBCH0 pins are
timer channel I/O pins or general-purpose I/O pins. See 18.8.1 TIMB Status and Control Register.
NOTE
Data direction register B (DDRB) does not affect the data direction of port
B pins that are being used by the TIMB. However, the DDRB bits always
determine whether reading port B returns the states of the latches or the
states of the pins. See Table 12-2.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
117