MC68HC908EY16 Datasheet, PDF (191/278 Pages) Motorola, Inc – Microcontrollers

16.5 TBM Interrupt Rate
The interrupt rate is determined by the equation:
t_TBMRATE
=
-----------1-------------
f_TBMRATE
=
-D----i--v---i--d----e----r
f_TBMCLK
TBM Interrupt Rate
where:
f_TBMCLK =Frequency supplied from the internal clock generator (ICG) module
Divider = Divider value as determined by TBR2–TBR0 settings.
See Table 16-1
As an example, a clock source of 4.9152 MHz and the TBR2–TBR0 set to {011}, the divider tap is 128
and the interrupt rate calculates to 128/4.9152 x 10⁶ = 26 µs.
Table 16-1. Timebase Divider Selection
TBR2⁽¹⁾
0
0
0
0
1
1
1
1
TBR1⁽¹⁾
0
0
1
1
0
0
1
1
TBR0⁽¹⁾
0
1
0
1
0
1
0
1
Divider Tap
TMBCLKSEL
0
1
32,768
4,194,304
8192
1,048,576
2048
262144
128
16,384
64
8192
32
4096
16
2048
8
1024
1. Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before executing the WAIT instruction.
16.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the internal clock
generator has been enabled to operate during stop mode through the OSCENINSTOP bit in the
configuration register. The timebase module can be used in this mode to generate a periodic wake up
from stop mode.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
191