MC68HC908EY16 Datasheet, PDF (90/278 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
8.4.3 Using Clock Monitor Interrupts
The clock monitor circuit can be used to recover from perilous situations such as crystal loss. To use the
clock monitor effectively, these points should be observed:
• Enable the clock monitor and clock monitor interrupts.
• The first statement in the clock monitor interrupt service routine (CMISR) should be a read to the
ICG control register (ICGCR) to verify that the clock monitor flag (CMF) is set. This is also the first
step in clearing the CMF bit.
• The second statement in the CMISR should be a write to the ICGCR to clear the CMF bit (write the
bit low). Writing the bit high will not affect it. This statement does not need to immediately follow
the first, but must be contained in the CMISR.
• The third statement in the CMISR should be to clear the CMON bit. This is required to ensure
proper reconfiguration of the reference dividers. This statement also must be contained in the
CMISR.
• Although the clock monitor can be enabled only when both clocks are stable (ICGS is set or ECGS
is set), it will remain set if one of the clocks goes unstable.
• The clock monitor only works if the external slow (EXTSLOW) bit in the CONFIG is set to the
correct value.
• The internal and external clocks must both be enabled and running to use the clock monitor.
• When the clock monitor detects inactivity, the inactive clock is automatically deselected and the
active clock selected as the source for CGMXCLK and TBMCLK. The CMISR can use the state of
the CS bit to check which clock is inactive.
• When the clock monitor detects inactivity, the application may have been subjected to extreme
conditions which may have affected other circuits. The CMISR should take any appropriate
precautions.
8.4.4 Quantization Error in DCO Output
The digitally controlled oscillator (DCO) is comprised of three major sub-blocks:
1. Binary weighted divider
2. Variable-delay ring oscillator
3. Ring oscillator fine-adjust circuit
Each of these blocks affects the clock period of the internal clock (ICLK). Since these blocks are controlled
by the digital loop filter (DLF) outputs DDIV and DSTG, the output of the DCO can change only in
quantized steps as the DLF increments or decrements its output. The following sections describe how
each block will affect the output frequency.
8.4.4.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock
(ICLK), whose clock period is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]).
Because of the digital nature of the DCO, the clock period of ICLK will change in quantized steps. This
will create a clock period difference or quantization error (Q-ERR) from one cycle to the next. Over several
cycles or for longer periods, this error is divided out until it reaches a minimum error of 0.202 percent to
0.368 percent. The dependence of this error on the DDIV[3:0] value and the number of cycles the error is
measured over is shown in Table 8-2.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
90
Freescale Semiconductor