MC68HC908EY16 Datasheet, PDF (233/278 Pages) Motorola, Inc – Microcontrollers

Monitor Module (MON)
MC68HC908EY16
V_DD
N.C.
RST
1 µF
1 µF
DB9
2
3
MAX232
V_DD
1 _C1+
+
3 _C1–
V_CC ¹⁶
GND ¹⁵
+
1 µF
1 µF
+
4 _C2+
+
5 _C2–
7
8
V+ ²
V– ⁶
10
9
1 µF
+
74HC125
6
5
74HC125
2
3
4
V_DD
10 kΩ
N.C.
10 k*
OSC1
IRQ
PTA0
5
1
* Value not critical
Figure 19-11. Forced Monitor Mode (IRQ = V_SS)
V_DD
V_DDA
0.1 µF
PTB4
N.C.
PTB3
N.C.
10 k
PTA1
V_SSA
V_SS
Enter monitor mode with pin configuration shown in Table 19-1 by pulling RST low and then high. The
rising edge of RST latches monitor mode. Once monitor mode is latched, the levels on the port pins
except PTA0 can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
19.3.1.1 Normal Monitor Mode
If V_TST is applied to IRQ upon monitor mode entry, the bus frequency is a divide-by-four of the input clock.
When monitor mode was entered with V_TST on IRQ, the computer operating properly (COP) is disabled
as long as V_TST is applied to either IRQ or RST.
This condition states that as long as V_TST is maintained on the IRQ pin after entering monitor mode, or if
V_TST is applied to RST after the initial reset to get into monitor mode (when V_TST was applied to IRQ),
then the COP will be disabled. In the latter situation, after V_TST is applied to the RST pin, V_TST can be
removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
233