MC68HC908EY16 Datasheet, PDF (82/278 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these
outputs on the capacitor size, current reference, and voltage reference causes up to ±25 percent error in
f_NOM.
8.3.2.4 Digital Loop Filter
The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock
(ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage
control bits (DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the DDIV and DSTG
registers (DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the relative error in the
low-frequency base clock’s period, as shown in Table 8-1. In some extreme error conditions, such as
operating at a V_DD level which is out of specification, the DLF may attempt to use a value above the
maximum ($9FF) or below the minimum ($000). In both cases, the value for DDIV will be between $A and
$F. In this range, the DDIV value will be interpreted the same as $9 (the slowest condition). Recovering
from this condition requires subtracting (increasing frequency) in the normal fashion until the value is
again below $9FF. (If the desired value is $9xx, the value may settle at $Axx through $Fxx. This is an
acceptable operating condition.) If the error is less than ±5 percent, the internal clock generator’s filter
stable indicator (FICGS) is set, indicating relative frequency accuracy to the clock monitor.
Table 8-1. Correction Sizes from DLF to DCO
Frequency Error
of IBASE Compared
to f_NOM
IBASE < 0.85 f_NOM
DDVI[3:0]:DSTG[7:0]
Correction
–32 (–$020)
Current to New
DDIV[3:0]:DSTG[7:0]⁽¹⁾
Minimum
Maximum
$xFF to $xDF
$x20 to $x00
Relative Correction
in DCO
–2/31
–2/19
–6.45%
–10.5%
0.85 f_NOM < IBASE
IBASE < 0.95 f_NOM
–8 (–$008)
Minimum
Maximum
$xFF to $xF7
$x08 to $x00
–0.5/31
–0.5/17.5
–1.61%
–2.86%
0.95 f_NOM < IBASE
IBASE < f_NOM
–1 (–$001)
Minimum
Maximum
$xFF to $xFE
$x01 to $x00
–0.0625/31
–0.0625/17.0625
–0.202%
–0.366%
f_NOM < IBASE
IBASE < 1.05 f_NOM
+1 (+$001)
Minimum
Maximum
$xFE to $xFF
$x00 to $x01
+0.0625/30.9375
+0.0625/17
+0.202%
+0.368%
1.05 f_NOM < IBASE
IBASE < 1.15 f_NOM
+8 (+$008)
Minimum
Maximum
$xF7 to $xFF
$x00 to $x08
+0.5/30.5
+0.5/17
+1.64%
+2.94%
1.15 f_NOM < IBASE
+32 (+$020)
Minimum
Maximum
$xDF to $xFF
$x00 to $x20
+2/29
+2/17
+6.90%
+11.8%
1. x = Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0]
carries or borrows.
8.3.3 External Clock Generator
The ICG also provides for an external oscillator or external clock source, if desired. The external clock
generator, shown in Figure 8-4, contains an external oscillator amplifier and an external clock input path.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
82
Freescale Semiconductor