MC68HC908EY16 Datasheet, PDF (160/278 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
14.3.2.6 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V_DD voltage falls to the V_TRIPF
voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the
LVIPWRD and LVIRSTD bits in the CONFIG register are at 0. The MCU is held in reset until V_DD rises
above V_TRIPR. The MCU remains in reset until the SIM counts 4096 CGMXCLK to begin a reset recovery.
Another 64 CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to
occur. See Chapter 11 Low-Voltage Inhibit (LVI) Module.
14.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of
CGMXCLK.
14.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the internal clock generator to drive the
bus clock state machine.
14.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration
register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles.
14.4.3 SIM Counter and Reset States
The SIM counter is free-running after all reset states. See 14.3.2 Active Resets from Internal Sources for
counter control and internal reset recovery sequences.
14.5 Program Exception Control
Normal, sequential program execution can be changed in two ways:
1. Interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
160
Freescale Semiconductor