MC68HC908EY16 Datasheet, PDF (216/278 Pages) Motorola, Inc – Microcontrollers

Timer Interface B (TIMB) Module
18.5 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby
modes.
18.5.1 Wait Mode
The TIMB remains active after the execution of a WAIT instruction. In wait mode, the TIMB registers are
not accessible by the central processor unit (CPU). Any enabled CPU interrupt request from the TIMB can
bring the MCU out of wait mode.
If TIMB functions are not required during wait mode, reduce power consumption by stopping the TIMB
before executing the WAIT instruction.
18.5.2 Stop Mode
The TIMB is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIMB counter. TIMB operation resumes when the MCU exits stop
mode.
18.6 TIMB During Break Interrupts
A break interrupt stops the TIMB counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
18.7 I/O Signals
Port B shares two of its pins with the TIMB. There is no external clock input to the TIMB prescaler. The
two TIMB channel I/O pins are PTB6/TBCH0 and PTB7/TBCH1. See Chapter 12 Input/Output (I/O) Ports
(PORTS).
18.7.1 TIMB Channel I/O Pins (PTB7/TBCH1–PTB6/TBCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTB6/TBCH0 and PTB7/TBCH1 can be configured as buffered output compare or buffered PWM pins.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
216
Freescale Semiconductor