MC68HC908EY16 Datasheet, PDF (178/278 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
BYTE 1
SPI RECEIVE
1
COMPLETE
SPRF
BYTE 2
5
BYTE 3
7
BYTE 4
11
OVRF
READ SPSCR
2
4
6
9
12
14
READ SPDR
3
8
10
13
1 BYTE 1 SETS SPRF BIT.
8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT.
2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR.
9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
3 CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT.
10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT.
4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
5 BYTE 2 SETS SPRF BIT.
12 CPU READS SPSCR.
6 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR.
13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT.
7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
Figure 15-8. Clearing SPRF When OVRF Interrupt Is Not Enabled
15.6.2 Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit (MODFEN in SPSCR) must be
set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again
after MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR)
is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure 15-9). It is not possible to enable
only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
SPTE SPTIE SPE
SPRIE SPRF
SPI TRANSMITTER
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 15-9. SPI Interrupt Request Generation
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
178
Freescale Semiconductor