MC68HC908EY16 Datasheet, PDF (161/278 Pages) Motorola, Inc – Microcontrollers

Program Exception Control
14.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the return-from-interrupt
(RTI) instruction recovers the CPU register contents from the stack so that normal processing can
resume. Figure 14-7 shows interrupt entry timing. Figure 14-8 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L STARTADDR
IDB
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
R/W
Figure 14-7. Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
IDB
CCR
A
X PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND
R/W
Figure 14-8. Interrupt Recovery
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. As shown in
Figure 14-9, once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless
of priority, until the latched interrupt is serviced or the I bit is cleared.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
161