MC68HC908EY16 Datasheet, PDF (165/278 Pages) Motorola, Inc – Microcontrollers

Figure 14-12 and Figure 14-13 show the timing for WAIT recovery.
Low-Power Modes
IAB
$DE0B
$DE0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$DE
EXITSTOPWAIT
Note: EXITSTOPWAIT = CPU interrupt
Figure 14-12. Wait Recovery from Interrupt
IAB
$DE0B
64
CYCLES
RST VCT H RST VCT L
IDB $A6 $A6
$A6
IRST
CGMXCLK
Figure 14-13. Wait Recovery from Internal Reset
14.6.2 Stop Mode
In stop mode, the SIM counter is held in reset and the CPU and peripheral clocks are held inactive. If the
STOPOSCEN bit in the configuration register is not enabled, the SIM also disables the internal clock
generator module outputs (CGMOUT and CGMXCLK).
The CPU and peripheral clocks do not become active until after the stop delay timeout. Stop mode is
exited via an interrupt request from a module that is still active in stop mode or from a system reset.
An interrupt request from a module that is still active in stop mode can cause an exit from stop mode. Stop
recovery time is selectable using the SSREC bit in the configuration register. If SSREC is set, stop
recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. Stacking for interrupts
begins after the selected stop recovery time has elapsed.
When stop mode is exited due to a reset condition, the SIM forces a long stop recovery time of 4096
CGMXCLK cycles.
NOTE
Short stop recovery is ideal for applications using canned oscillators that do
not require long startup times for stop mode. External crystal applications
should use the full stop recovery time by clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 14-14 shows stop mode entry timing.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
165