MC68HC908EY16 Datasheet, PDF (197/278 Pages) Motorola, Inc – Microcontrollers

Functional Description
17.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTD0/TACH0 pin. The TIMA channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and
channel 1. The output compare value in the TIMA channel 0 registers initially controls the output on the
PTD0/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors
the buffered output compare function, and TIMA channel 1 status and control register (TASC1) is unused.
While the MS0B bit is set, the channel 1 pin, PTD1/TACH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
17.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM
signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 17-3 shows, the output compare value in the TIMA channel registers determines the pulse
width of the PWM signal. The time between overflow and output compare is the pulse width. Program the
TIMA to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the
TIMA to set the pin if the state of the PWM pulse is logic 0.
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
PTDx/TCHx
PULSE
WIDTH
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 17-3. PWM Period and Pulse Width
OUTPUT
COMPARE
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
197